I/O and Storage

This USB online training course focuses on system definition including the USB component. The USB communication model will be studied and transactions will be evaluated in detail. Bandwidth allocations, packet types, packet protocols, and packet sequencing are also covered. USB 2.0 Architecture Part 1 also covers device framework including device descriptors and device requests.

Once you have completed USB 2.0 Architecture Part 1 the next course in this series is USB 2.0 Architecture Part 2. USB Architecture Part 2 discusses in more detail low-speed, full-speed and high-speed environments. Presentations include the encoding and electrical environment, evaluating descriptors and host requests, and On-The-Go protocol. Click here to learn more about USB 2.0 Architecture Part 2.

Download the course outline.

Module 00: Course Introduction

Module 01: History and Overview

• Problem Solved by USB
• USB Specification History
• USB Features
• Hot Plug, Isochronous Bandwidth, Error Handling/Fault Recovery

Module 02: System Description

• System Description and Configuration
• USB Components
• Topologies
• Attachment/Removal of USB Devices

Module 03: Architectural Overview

• Bus Enumeration
• Physical Interface
• USB Protocol
• Transactions

Module 04: Communications Flow

• Host-client Relationship
• Device End Point
• Pipes
• Frames
• In and Out Transactions

Module 05: Bus Transfers

• Transfer types
• Transaction Examples for Each Type
• Bus Access for Transfers
• Bus Bandwidth Reclamation

Module 06: Packet Types and Formats

• Packet Field Formats
• Token Packets
• Data Packets

Module 07: Packets and Packet Sequencing

• Hand Shake Packets
• Special Token Packets
• NAK and Ping

Module 08: Packet Protocol

• Bulk, Control, Interrupt, and Isochronous
• Synchronization and Re-try
• Packet Errors
• Bus Errors

Module 09: Device Framework

• Device Class Definitions
• Standard Descriptors
• USB Device Operation
• Power Management

Module 10: USB Device Requirements

• Device Request Types
• Class Specific Requests
• Vendor Specific Requests

Module 11: USB Host Requirements

• Host Controller Requirements
• Device Drivers
• Resource Management

Module 12: Course Summary

An understanding of serial communications techniques is also highly recommended.

USB Architecture Part 2 online training gets into more detail covering low-speed, full-speed and high-speed environments. You will learn about the encoding and electrical environment including differential signaling. USB configuration will be explored in detail, including evaluating descriptors, and host requests in this online training. You will also learn about the On-The-Go protocol.

In order to take this course you need to have taken USB 2.0 Architecture Part 1 and have an understanding of serial communications techniques.

Once you have completed USB 2.0 Architecture Part 1 and Part 2 the next recommended course is USB 3.0 Architecture Update. The USB 3.0 Architecture Update course will discuss the most current knowledge of the third generation of USB - SuperSpeed USB. Presentations will include a thorough examination of the increased transfer rates to 5.0Gbps, improved flow control and power management, as well as the changes to the protocol layers. Click here to learn more about USB 3.0 Architecture Update.

Download the course outline.

Module 00: Course Introduction

Module 01: USB Hub Requirements

• Architecture
• Transaction Translator
• Hub Controller
• Descriptors and Requests

Module 02: Low-Speed and High-Speed Environments

• Overview
• Device Detection
• SOP/EOP

Module 03: Low-Speed and Full-Speed Transfers

• Encoding
• Transfer Types
• Error Recovery

Module 04: High-Speed Overview

• Device Detection
• Differential Signaling
• Drivers and Receivers
• Reset and Suspend

Module 05: High Speed Transfers

• Periodic
• Non-Periodic
• Error Recovery

Module 06: Split Transactions

• Split Token Packet
• Transaction Translator
• Scheduling

Module 07: Configuration Overview

• Configuration Process
• Reading and Evaluating Descriptors
• Device Descriptors
• Device_qualifer Descriptor

Module 08: Device Descriptors and States

• Configuration, Speed, and Interface Descriptors
• Evaluating Descriptors
• Device States

Module 09: Hub Configuration

• Reading and Evaluating Descriptors
• Hub Class Descriptors
• Hub and Port Status
• Hub Power

Module 10: On-The-Go Overview

• Definitions
• Features
• Mechanical Specifications

Module 11: On-The-Go Protocols

• Electrical Specifications
• Session Request Protocol
• Host Negotiation Protocol

Module 12: Course Summary

Attendees are expected to have a good understanding of serial communications techniques and have taken USB 2.0 Architecture Part 1.

In this USB 3.0 Architecture Update online training course you will gain the most current knowledge of the third generation of USB - SuperSpeed USB. We will thoroughly examine the increased transfer rates to 5.0Gbps, improved flow control and power management, as well as the changes to the protocol layers. USB 2.0 is briefly reviewed because USB 3.0 is required to be completely backwards compatible.

Download the course outline.

Module 00: USB 3.0 Architecture Update Course Introduction

Module 01: USB 2.0 Overview Part 1

• Device, Hosts, and Hubs
• USB 2.0 Topology
• o Physical Layer
  o Link Layer
  o Protocol Layer
• USB Transfer Types

Module 02: USB 2.0 Overview Part 2

• Error Handling
• Communication Model-Transactions

Module 03: USB 2.0 Transfers

• Control Transfers
• Interrupt Transfers
• Bulk Transfers

Module 04: Packets and Descriptors

• Packets and Packet Type
• Descriptors

Module 05: USB 2.0 Configuration

• Power Management
• Device Detection-Signaling
• Differential Signaling

Module 06: USB 3.0 Architecture

• Support for USB 2.0
• USB 3.0 Architecture Overview
• System Description

Module 07: Data Flow Model

• USB 3.0 Transfers
• o Types
  o Data Bursting
• Transaction Protocol Improvements

Module 08: Physical Layer

• Transmitter/Receiver Requirements
• Data Scrambling
• Encoding
• LFPS
• Mechanical requirements

Module 09: Link Layer

• Packets
• Flow control and Link Management
• LTSSM
• State Diagrams
• Resets

Module 10: Protocol Packets Part 1

• Packet formats
• o Link Management Packets
  o Transaction Packets

Module 11: Protocol Packets Part 2

• Packets
• Device Notification
• Data Packets
• Format and Sequencing

Module 12: Transfers Part 1

• Transactions
• Data Bursting
• Bulk Streaming

Module 13: Transfers Part 2

• Interrupt Transfers
• Sequencing
• Isochronous Transfers

Module 14: Device States and Enumeration

• Device States
• Device Operation
• Eumeration

Module 15: Request and Descriptors

• Device Requests
• Device Descriptors
• o New to 3.0
  o Modified 2.0

Module 16: Hubs

• Hub Architecture
• o State Machine
  o Repeater/Forwarder
• Packet Routing
• Resume Signaling

Module 17: Power Management

• Link power management
• Device PM
• Hub PM
• Suspend/Resume
• Latency Tolerance Message

Module 18: UAS

• History of Bulk
• Goals for UAS
• Transfers

Module 19: Data Traffic Analysis

• Link Control
• IN and OUT transactions
• Packets
• Demo

You need to have equivalent experience or have taken the following GogoTraining courses:

• USB 2.0 Architecture Part 1
• USB 2.0 Architecture Part 2

This PCI Express (PCIe) online training course is intended to be an overview to PCI Express for design engineers, testing, manufacturing and verification engineers. The topics discussed in the PCIe training modules include an architectural overview and history of PCI Express, the layers and virtualization.

Module 00: Course Introduction

Module 01 - PCI Evolution

• Specification History
• PCIe Compatibility
• Protocol Stack
• New Features

Module 02 - PCIe Architectural Overview (Part 1)

• PCIe Commands
• Devices
• Traffic Prioritization

Module 03 - PCIe Architectural Overview (Part 2)

• Root Complex
• PCIe Link Overview
• PCIe Configuration

Module 04 - PCIe Transaction Layer

• Functional Requirements
• TLPs
• Address Space
• Flow Control

Module 05 - Data Link Layer

• Functional Requirements
• DLLPs
• State Machine
• Link Initialization

Module 06 - Physical Layer

• Logical and Electrical Sub-blocks
• Differential Signaling
• Control Signaling

Module 07 - Virtual Channels

• Arbitration
• Capabilities Structure

Module 08 - Virtualization Overview

• CPU vs. Platform
• PCIe's Implementation of Virtualization
• Single- and Multi-Root I/O Virtualization

Module 09: Course Summary

An understanding of PCI is desired, but not required.

In this PCI Express (PCIe) Architecture online training course, you will learn about the key features of the PCI-SIG‘s specifications from PCI foundations all the way to, and including, the latest version 3.0 changes/enhancements. You will learn about Legacy and native PCI Express devices and how the new features of PCIe can be supported whilst still providing compatibility with legacy PCI devices and software.

We will discuss the details of the PCI Express protocol stack for Express devices, including the three protocol layer functions and formats and their configuration requirements. You will learn about the latest protocol enhancements that are required to support the new Gen3 speed of 8GT/s. These include the 128/130b encoding schemes, block formats and new equalization procedures.

We will also overview the new features added to the PCIe specification – such as Multicast, Access Control Services, Alternative Routing ID Interpretation, Advanced Error Reporting, Address Translation Services, Optimized Buffer Flush/Fill, Latency Tolerance Reporting, M-PCIe and Readiness Notifications. We will also discuss Signal Integrity and the challenges that the new speeds of PCIe bring to board layout, as well as I/O virtualization and multi host resource sharing.  

Module 00: PCI Express Gen 1 to Gen 3 Architecture - Course Introduction

Module 01:  PCI Evolution

• PC I/O History
• PCIe Compatibility
• PCIe Features

Module 02:  PCI Commands, Bus Operations and Device Types

• PCI Commands and Transactions
• PCIe Packets
• PCIe Waveform
• PCI Commands, Bus Operations and Device Types Quiz

Module 03: Bridges, Switches, Arbitration and Interrupts

• PCI Arbitration
• PCIe Switch Structure
• Interrupts

Module 04: Error Handling, Signaling Environments and Address Spaces

• Error Reporting Methods
• Link Attributes
• Understanding Bandwidth
• Configuration Headers
• Bridge, Switches and Address Spaces Quiz

Module 05: Configuration Space

• Configuration Space Model
• PCIe Capability Structure
• Root Complex

Module 06: Bridge Discovery

• Switch Config Space Compatibility
• PCI Type 1 to Type 0 Conversion
• Configuration Space Probing
• Bridge Discovery and Capability Structure Quiz

Module 07: Configuration Methods

• Bus Enumeration
• Base Limit Registers
• Address Routing
• ID Routing

Module 08: Configuration Registers

• Register Attributes
• Header Types
• Extended Capability Structures
• Optional Registers
• Enumeration Workshop and Configuration and PCIe Routing Quiz

Module 09: Transaction Layer Protocol Part 1

• Overview of TLP Transactions
• TLP Packet Components
• TLP Packet Components
• TLP Headers

Module 10: Transaction Layer Protocol Part 2

• TLP Fmt Encoding
• TLP Attributes
• Error Poisoning
• Data Payloads
• Transaction Descriptor

Module 11: Transaction Layer Protocol Part 3

• Byte Enable Rules
• TLP Addressing
• Completion Rules
• Transaction Layer Protocol Quiz

Module 12: MSI and Messages

• Message Codes and Rules
• Error Signaling
• Post and Non-Posted Transactions

Module 13: Transaction Ordering, Virtual Channels and Flow Control

• PCIe Ordering Rules
• Virtual Channel Mapping
• PCIe Flow Control Overview
• Completion Time Out
• Transaction Ordering, Virtual Channels and Flow Control Quiz

Module 14: Data Link Layer Part 1

• DLLP Construction
• DLL Control
• Initialization Flow Control

Module 15: Data Link Layer Part 2

• DLLP Header
• DLL Services
• DLL Flow Control

Module 16: Data Link Layer Part 3

• Normal Operations
• TLP Conditioning
• Sequence Numbering
• Replay Timer
• Data Link Layer Quiz

Module 17: Physical Layer Part 1

• Sub-Block Overview
• Scrambling
• Encoding
• Link Initialization

Module 18: Physical Layer Part 2

• PCIe Signaling
• Byte Striping
• Lane Assignments
• Polarity and Lane Reversal
• Physical Layer Quiz

Module 19: Serial Versus Parallel Communications

• Review of Parallel Systems
• Serial Signaling
• Graphics Review
• Layered Protocols Stacks OSI

Module 20: Layered Protocols Stacks PCIe

• PCIe Layers
• Error Detection Within Layers
• PCIe Mapping Comparison
• PCIe and Switches
• Signaling, Stacks and Switches Quiz

Module 21: Serial Protocol Analyzers

• Test Verification Tools
• Serial Testing
• Protocol Analyzer Characteristics
• PCIe Compliance

Module 22: Link Training and Status State Machine (LTSSM)

• LTSSM Overview
• LTSSM Link Initialization
• LTSSM Sub-States
• Link Speed Change

Module 23: LTSSM Power Management

• PCIe Link PM State Diagram
• PCIe PM Link States
•  PCI Power Management Compatibility
• Transitioning to Low Power States
• LTSSM Quiz

Module 24: Virtual Channels Differentiated Services

• Virtual Channels Overview
• Traffic Classes
• Arbitration Methods
• Register Sets Details

Module 25: Virtual Channels Examples

• Arbitration Examples
• Traffic Class Virtual Channel Mapping Example
• Traffic Class Filtering
• Link Multiplexing
• Isochronous Traffic Example
• Virtual Channels Quiz

Module 26: System Issues and Features

• Initialization and Enumeration Review
• Error Signaling and Logging
• Error Classifications
• PCIe Resets

Module 27: Hot Plug Power Management and Interrupts

• Hot Plug Elements
• Hot Plug Card Removal and Insertion Example
• PCIe Power Management
• PCIe Interrupts
• Handling Legacy Interrupts
• Message Signal Interrupts
• Hot Plug,  Power Management and Interrupts Quiz

Module 28: Electrical and Mechanical Requirements

• Card Electro Mechanical Specification Overview
• Adding Cards
• Card Interoperability
• Card Form Factors
• Routing Considerations
• PCIe Clocking

Module 29: I/O Virtualization in PCIe Overview Part 1

• IOV Definitions
• Connecting Multiple Hosts Together
• Options and Issues

Module 30: I/O Virtualization in PCIe Overview Part 2

• Muli-Root  (MR-IOV)
• Single-Root (SR-IOV)
• Non Single-Root IOV
• I/O Virtualization in PCIe Quiz

Module 31: PCIe Gen3 Protocol Enhancements

• Protocol Overview
• Compatibility
• Encoding Revision
• Gen3 Encoding
• Data Blocks
• Framing Tokens

Module 32: Gen3 Block Alignment and Scrambling

• Ordered Set Blocks
• Block Phases
• Framing Requirements
• Block Framing Examples
• Scrambling
• Error Detection and Recovery
• Gen3 Protocol and Encoding Quiz

Module 33: LTSSM Updates

• LTSSM Review
• Recovery and Support for Gen3
• Gen3 Equalization Training Sequence
• Gen3 Equalization Phase
• Testability Features

Module 34: Gen3 Equalization Phase

• Gen3 Equalization
• Gen3 Equalization Phase Details
• Gen3 Equalization Phase Summary
• Gen3 Equalization Phase Quiz

Module 35: Gen3 Signal Integrity Overview

• Gen3 Signal Challenges
• Gen3 Filtering and Equalization
• Board Layout Considerations
• Gen3 Signal Integrity Quiz

Module 36: PCIe Gen2/3 Protocol Enhancements Overview Part 1 

• Multicast
• Access Control Services
• Alternative RoutingID Interpretation (ARI)
• AER

Module 37: PCIe Gen2/3 Protocol Enhancements Overview Part 2 

• Address Translation Services
• Optimized Buffer Flush/Fill (OBFF)
• Latency Tolerance Reporting (LTR)
• Downstream Port Containment (DPC)
• Separate Refclk with Independent SSC (SRIS)
• M-PCIe
• Readiness Notifications (RN)
• PCIe Gen2/3 Protocol Enhancements Quiz

Participants should have an understanding of how parallel and serial bus systems are used in PC systems and although knowledge of the PCI and PCIe specifications is beneficial it is not a requirement.